Why this course?

Description

The Advanced VLSI Design & Verification Masterclass is a hands-on program designed to equip you with industry-ready skills in SystemVerilog, UVM, and advanced verification methodologies. From mastering RTL design principles to implementing and verifying complex protocols like AMBA, you’ll learn through practical sessions, projects, and real-world case studies. This masterclass prepares you to confidently design, simulate, and verify cutting-edge digital systems—paving the way for a successful career in the semiconductor industry.

Agenda:

Week-1:Foundation (Computer Architecture + Digital Electronics)
Day 1 – Introduction to VLSI & Course Roadmap (Frontend vs Backend, RTL                 vs Verification)
Day 2 – Basics of Computer Architecture (ISA, CPU, Memory hierarchy, Buses)
Day 3 – Digital Electronics Part-1 (Logic gates, K-map, Combinational circuits)
Day 4 – Digital Electronics Part-2 (Sequential circuits, FF, Latch, Counters,                      FSM intro)
Day 5 – FSMs Deep Dive (Moore vs Mealy, State diagrams → RTL design)
Day 6 – Timing Concepts (Setup/Hold, Clock Skew, STA basics)
Day 7 – Overview of Verilog and timing region of Verilog.

Week-2 : SystemVerilog Basics (Design + Verification Start)
Day 8 – SystemVerilog for RTL (Data types, Operators, always_comb,                              always_ff)
Day 9 – SystemVerilog for Verification (Classes, OOP, Randomization basics)
Day 10 – Mailbox, Queue, Event, Semaphores in SV
Day 11 – Testbench Architecture (Stimulus, Monitor, Scoreboard, Coverage)
Day 12 – Assertions ( SVA Basics)
Day 13 – Immediate & Concurrent Assertions.
Day 14 – Mini Project: UART RTL + Testbench (Code)

Week 3: Advanced RTL Design & Verification
Day 15 – Memory Design: Single-port/ Dual-port RAM (RTL + TB)
Day 16 – FIFO Design & Verification (Asynchronous FIFO, CDC basics)
Day 17 – Clock Domain Crossing (CDC techniques: Synchronizers)
Day 18 – constraints in system verilog
Day 19 – Mini Project: I2C Spec Discussion
Day 20 – Mini Project: I2C RTL + Verification Testbench

Week-4 : AMBA Protocols + Major Projects
Day 21 – AMBA Overview (APB, AHB, AXI introduction, timing diagrams)
Day 22 – APB Protocol – Part 1 (SPECIFICATION)
Day 23 – APB Protocol – Part 2 (CODE IMPLEMENTATION)
Day 24 – AHB Protocol – Part 1 (Read channel, bursts, VALID/READY                                handshake)
Day 25 – AHB Protocol – Part 2 (Write channel, response, ordering rules and                  code)
Day 26 – AXI Protocol – Part 1 (Read channel, bursts, VALID/READY                                  handshake)
Day 27 – AXI Protocol – Part 2 (Write channel, response, ordering rules)
Day 28 – AXI Protocol – Coding Day (RTL + Verification TB)
Day 29 – SystemVerilog Coverage & Assertions for Protocol Verification                          (APB/AXI)
Day 30 – Final Wrap-Up + Career Guidance in VLSI + Live Q&A

Tools covered :

• Questa
• EDA

Project covered :

• UART SPEC & RTL + TESTBENCH
• APB PROTOCOL – SPEC, DESIGN & VERIFICATION CODE
• I2C SPEC & RTL DESIGN
• AHB PROTOCOL – READ/WRITE CHANNELS, BURSTS, HANDSHAKE, RTL & VERIFICATION